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...the world's most energy friendly microcontrollers
cycle_ctrl
b010
b011
b100
b101
b110
b111
Description
Auto-request
Ping-pong
Memory scatter-gather using the primary data structure
Memory scatter-gather using the alternate data structure
Peripheral scatter-gather using the primary data structure
Peripheral scatter-gather using the alternate data structure
For all cycle types, the controller arbitrates after 2 DMA transfers. If you set a low-priority channel with
a large 2 value then it prevents all other channels from performing a DMA transfer, until the low-priority
1. The controller performs 2 transfers. If the number of transfers remaining is zero the flow continues
1. The controller performs 2 transfers for channel C. If the number of transfers remaining is zero the
Note
The cycle_ctrl bits are located in the channel_cfg memory location that Section 8.4.3.3 (p.
53) describes.
R
R
DMA transfer completes. Therefore, you must take care when setting the R_power, that you do not
significantly increase the latency for high-priority channels.
8.4.2.3.1 Invalid
After the controller completes a DMA cycle it sets the cycle type to invalid, to prevent it from repeating
the same DMA cycle.
8.4.2.3.2 Basic
In this mode, you configure the controller to use either the primary, or alternate, data structure. After you
enable the channel, and the controller receives a request then the flow for this DMA cycle is:
R
at step 3 (p. 43) .
2. The controller arbitrates:
? if a higher-priority channel is requesting service then the controller services that channel
? if the peripheral or software signals a request to the controller then it continues at step 1 (p. 43) .
3. The controller sets dma_done[C] HIGH for one HFCORECLK cycle. This indicates to the host
processor that the DMA cycle is complete.
8.4.2.3.3 Auto-request
When the controller operates in this mode, it is only necessary for it to receive a single request to enable
it to complete the entire DMA cycle. This enables a large data transfer to occur, without significantly
increasing the latency for servicing higher priority requests, or requiring multiple requests from the
processor or peripheral.
You can configure the controller to use the primary, or alternate, data structure. After you enable the
channel, and the controller receives a request for this channel, then the flow for this DMA cycle is:
R
flow continues at step 3 (p. 43) .
2. The controller arbitrates. When channel C has the highest priority then the DMA cycle continues at
step 1 (p. 43) .
3. The controller sets dma_done[C] HIGH for one HFCORECLK cycle. This indicates to the host
processor that the DMA cycle is complete.
8.4.2.3.4 Ping-pong
In ping-pong mode, the controller performs a DMA cycle using one of the data structures and it then
performs a DMA cycle using the other data structure. The controller continues to switch from primary to
2011-04-12 - d0001_Rev1.10
43
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